Addressing of memory matrix
US6950330B2 · kind B2 · utility
10Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2004 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Sep 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.