Memory bit line leakage repair
US6950359B2 · kind B2 · utility
3Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2003 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Jul 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for replacing and eliminating paths causing channel leakage current. In one embodiment, one or more precharge enable transistors and a precharge enable signal are added to a circuit configuration. The precharge enable transistors are designed to remain on and simply pass a signal in a properly functioning path. When a leakage path is identified, such as during IDDQ testing, the precharge enable signal is set to turn off the precharge enable transistors. When the precharge enable transistors are off, the leakage path is disrupted, and the leakage current stopped. The path may be replaced with a redundant path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.