Modems utilizing low density parity check codes
US6950461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2001 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Jun 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2602
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A modem includes an LDPC encoder which utilizes a deterministic H-matrix, optionally via a generation matrix, to generate redundant parity bits for a bit block. Ones are placed into the H-matrix in a completely diagonal manner with diagonals subdivided into sets of diagonals. The first diagonal in each set i begins with coordinates H(1,k), where k=(1+(i*Mj)). The remaining diagonals in the sets are offset from the first diagonals so that the column distances between any two pairs of diagonals is unique. In another embodiment, the H-matrix is determined by assigning “1s” in a first column, and then assigning “1s” of subsequent columns deterministically by causing each “1” in a previous ancestor column to generate a “1” in the next descendant column based on the rule that a descendant is placed one position below an ancestor except where rectangles would be generated. Interrupted descending diagonals are generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.