Receiver having automatic burst mode I/Q gain and phase balance
US6950480B2 · kind B2 · utility
11Cited by
3References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2003 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | May 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/30
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for balancing I/Q gain and I/Q phase in a signal receiver. The receiver includes an IQ coefficient calculator, an IQ balancer, and a latency time delay device. The latency time delay device delays I and Q signals by a latency time period. During the latency time the IQ coefficient calculator uses the I and Q signals during a section of the packets corresponding to the latency time period for computing correction coefficients. The IQ balancer receives the I and Q signals after the latency time period and applies the correction coefficients to the entire packet of I and Q signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.