Method and apparatus for calibration of a delay element
US6950770B2 · kind B2 · utility
0Cited by
14References
21Claims
0Family size
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Key dates
| Filing date | Sep 25, 2002 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Sep 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00234
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various methods, systems and apparatuses having an integrated circuit that contains a calibration circuit having a series of delay elements to receive a reference signal. The reference signal establishes a standard unit of time. The calibration circuit also generates one or more calibrated delay signals derived from the reference signal. The one or more calibrated delay signals are precise to a known fraction of the standard unit of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.