Acceleration of convergence rate with verified bits in turbo decoding
US6950975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2002 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Nov 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
System and method for accelerating the convergence rate of turbo decoding by verifying bits in data frames whose CRC shows no bit errors. Verified bits are translated to bound nodes on a trellis of nodes representing a sequence of bits of the encoded code block. Verification of all bits signals a stop condition and decoding iterations can be terminated. Further, state transition metrics are limited when a node is adjacent to a bound node, allowing for acceleration of convergence by elimination of impossible state transitions. Also disclosed is a scheme to detect bit errors when the code block contains unframed data or partial data frames. This bit error detection scheme uses a recursive encoder to establish end node status. The end node state determination accelerates convergence rate recognition when incorporated with other stop conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.