Method for analysis of interconnect coupling in VLSI circuits
US6951001B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 2002 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | May 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/66
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for analyzing coupling between interconnects in a VLSI processor to simulate the impact of process variations by the use of model-fitted equations to determine a delay change curve for a coupled interconnect. Simulated curves are first used to determine the parameters in the model-fitted equations. These model-fitted equations are then used to derive the output waveform at the output of a victim line using superposition of noise waveforms calculated for a plurality of aggressors. The output waveform is then quadratically expanded to obtain the delay change curve, and the statistical mean and the standard deviation of the victim delay through the coupled interconnect are calculated by using said quadratic function and the statistical behavior of all inputs to the coupled interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.