Charge pump circuit for a PLL
US6952126B2 · kind B2 · utility
11Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2003 |
| Grant date | Oct 4, 2005 |
| Priority date | — |
| Expiry date | Jun 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0895
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.