Demapping system and method
US6952458B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2001 |
| Grant date | Oct 4, 2005 |
| Priority date | — |
| Expiry date | Dec 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/38
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A demapping system and method for demapping symbols into bits, is provided. An embodiment of the system comprises a processor, and a memory that is coupled to the processor. The memory comprises a memory module that comprises a program that finds a hard demapper output d based on a received symbol r; finds a challenger ci for each i, the challenger ci is a challenger of the hard demapper output d, i is an integer whose maximum value is a number of bits of the challenger ci; calculates reliability mi for each i, the reliability mi is the reliability of the hard demapper output d; and calculates soft bit xi for each i, the soft bit xi is calculated based on the reliability mi.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.