Digital signal processor update of single channel strength signal
US6952571B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2001 |
| Grant date | Oct 4, 2005 |
| Priority date | — |
| Expiry date | Jul 20, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and system of periodically measuring the signal strength fluctuations in a wireless connection between a portable computer system and a wireless network. The portable computer system has a main processor and a DSP (digital signal processor). The DSP receives instructions from the main processor for controlling the periodic measuring, and subsequent thereto is placed in low power mode. The main processor is placed into a low power mode after sending the instructions. The DSP periodically awakens to measure the signal strength fluctuations while the main processor remains in a low power mode. When the signal strength fluctuation is unacceptable, this triggers the DSP to awaken the main processor. When the signal strength fluctuation is acceptable, the DSP returns to a low power state until the next periodic measuring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.