System and method for predicting cache performance
US6952664B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2001 |
| Grant date | Oct 4, 2005 |
| Priority date | — |
| Expiry date | Oct 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and methods for simulating the performance (e.g., miss rate) of one or more caches. A cache simulator comprises a segmented list of buffers, with each buffer configured to store a data identifier and an identifier of the buffer's segment. Data references, which may be copied from an operational cache, are applied to the list to conduct the simulation. Initial estimates of each cache's miss rate include the number of references that missed all segments of the list plus the hits in all segments not part of the cache. A correction factor is generated from the ratio of actual misses incurred by the operational cache to the estimated misses for a simulated cache of the same size as the operational cache. Final predictions are generated by multiplying the initial estimates by the correction factor. The size of the operational cache may be dynamically adjusted based on the final predictions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.