Method and apparatus for verifying the integrity of control module operation
US6952795B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2001 |
| Grant date | Oct 4, 2005 |
| Priority date | — |
| Expiry date | Jul 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control module (100) includes a first signal processing unit (102) that is coupled to a second signal processing unit (114) by a control bus (130), an address bus (131) and a data bus (132). The control module conveys seed value addresses (108) and expected result addresses (110) over the address bus, seed values (118) and verification set output values (107) over the data bus, and compares each verification set output value to an expected result (120), thereby allowing the control module to determine whether the first signal processing unit, the control bus, the address bus, and the data bus are collectively functioning correctly. By properly selecting the seed value addresses, expected result addresses, seed values, and expected results (and correspondingly, verification set output values), proper operation of each line of the address bus and control bus may be individually verified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.