CMOS image sensor having reduced numbers of column readout circuits
US6953923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2003 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Oct 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The image sensor includes a first group and a second group of column readout circuits for reading out pixel signals from said pixels. The total number of column readout circuits in each group is substantially less than the number of columns in the image sensor pixel array. Further included is a multiplexer bus system having selection switches for selectively switching pixel signals from a block of pixels in a column as input into the first group of column readout circuits. The multiplexer bus system also selectively switches pixel signals from another block of pixels in a column as input into a second group of column readout circuits. However, when the first group of column readout circuits is reading and storing said pixel signals, the second group of column readout circuits is transferring out the processed signals. Thus, the first and second groups work alternately.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.