Link-layer receiver
US6954466B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2003 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Sep 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A System Packet Interface (SPI) level 4 receiver groups four consecutive 16 bit control/data words into a single 64 bit word (with a resultant rate of up to 210 MHz). The 64 bit word is processed for storage in a dual memory structure comprising two first-in-first-out (FIFO) memories for storing 64 bit words, wherein the 64 bit word may be stored in one, or both, of the FIFOs. The SPI-4.2 receiver issues commands that control subsequent processing of the 64 bit words (e.g., for alignment) using three types of commands, which are based on the relative temporal position of control words in the received data. Temporally, these commands are characterized as: PRE-COMMANDS, POST-COMMANDS and PRESENT-COMMANDS. A parallel general and selection method (PGSM) is used for FIFO Write Command Generation and for Diagonally Interleaved Parity (DIP-4) checking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.