Reconfigurable instruction set computing
US6954845B2 · kind B2 · utility
49Cited by
29References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2003 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Dec 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for adding reconfigurable computational instructions to a reduced instruction set computer. A computer program contains instruction extensions not native to the instruction set of the processor core and is loaded into an instruction memory accessible by the processor core of the computer. The computer program is then detected for containing the instruction extension. The programmable logic device is then configured to execute the instruction extension. The programmable logic device then executes the instruction extension for use by the processor core in processing the computer program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.