Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately
US6954848B2 · kind B2 · utility
2Cited by
3References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2002 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Feb 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.