Reduced verification complexity and power saving features in a pipelined integrated circuit
US6954865B2 · kind B2 · utility
4Cited by
5References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 18, 2002 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Dec 3, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit that uses a functional unit that outputs one set of values when in a power saving mode is provided. The functional unit, generally pipelined, is capable of being in the power saving mode dependent on an instruction decode/issue unit, and when in the power saving mode, the functional unit, using power saving mode circuitry, outputs one set of values as seen by components external to the functional unit regardless of the state the functional unit is in when the functional unit is initially put in the power saving mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.