Method and apparatus for coding bits of data in parallel
US6954885B2 · kind B2 · utility
15Cited by
20References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2001 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Jun 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for encoding multiple bits in parallel wherein outputs are generated recursively. During each clock cycle, the encoder processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units, which are then each uniquely addressed to provide data to parallel encoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.