Method for dicing wafer stacks to provide access to interior structures
US6955976B2 · kind B2 · utility
8Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2002 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Sep 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for dicing wafer stacks are provided. Preferably, the method includes the steps of: (1) providing a wafer stack having a first wafer and a second wafer; (2) exposing a portion of the first wafer by removing a portion of the second wafer; and (3) dicing the exposed portion of the first wafer such that a first die assembly is at least partially separated from the wafer stack. Wafer stacks and die assemblies also are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.