EMI grounding pins for CPU/ASIC chips
US6956285B2 · kind B2 · utility
16Cited by
38References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2003 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Jan 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package includes EMI containment features. The EMI containment features may include a plurality of pins on a substrate of the integrated circuit package. The pins may be a peripheral row of pins in an array of pins. The pins may couple a lid of the package to at least one ground plane of a circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.