Differential input buffers with elevated power supplies
US6956401B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2003 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Jan 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Input buffer circuitry for handling high-speed differential input signals on an integrated circuit is provided. The input buffer circuitry may use two parallel differential input buffers with overlapping input-voltage ranges. Logic on the integrated circuit may be powered at a core-logic power supply voltage. Input-output circuitry on the integrated circuit may be powered at an input-output voltage level. To improve the performance of the input buffers in the overlap range, at least one the input buffers can be powered using a total power supply voltage drop that exceeds the core-logic power supply level. One of the input buffers may be configured to handle lower-voltage input signals. This input buffer may be powered using the input-output power supply level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.