Powerup control of PLL
US6956416B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2004 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Feb 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic device, such as a microprocessor, with a timing circuit. The timing circuit contains a phase locked loop that, during a first interval, checks whether a control signal in the phase locked loop is between a maximum allowed value and a minimum allowed value. When the control signal in the phase locked loop is above a maximum allowed value or below a minimum allowed value, the control circuit disables the phase locked loop for a second interval. When the control signal in the phase locked loop is below a maximum allowed value and above a minimum allowed value, the timing circuit indicates that the output of the phase locked loop is stable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.