Fail-safe zero delay buffer with automatic internal reference
US6956419B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2004 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Apr 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may comprise a control circuit and an oscillator. The control circuit may be configured to generate a control signal in response to a first reference signal and a second reference signal. The oscillator may be configured to generate the second reference signal in response to the control signal and a timing signal. The control signal is generally held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled delay with respect to the first reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.