Slave-less edge-triggered flip-flop
US6956421B1 · kind B1 · utility
5Cited by
9References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 10, 2003 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Jul 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An edge-triggered flip flop includes a clocking portion having first and second transistor stacks that are coupled to first and second storage nodes of a memory element, respectively. In at least one embodiment, a clock signal is applied to an input of at least one transistor in each stack and a delayed and possibly inverted version of the clock signal is applied to an input of at least one other transistor in each stack to clock new data into the memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.