Cycle ready circuit for self-clocking memory device
US6956789B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2003 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Dec 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.