Controlled shared memory smart switch system
US6956861B2 · kind B2 · utility
6Cited by
17References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2002 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Jun 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3027
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interconnect structure comprising a plurality of input ports and a plurality of output ports with messages being sent from an input port to a predetermined output port through a switch S. Advantageously, the setting of switch S is not dependent upon the predetermined output port to which a particular message is being sent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.