System and method for encoding DSL information streams having differing latencies
US6956872B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2001 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Apr 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention is generally directed to a system and method for encoding a DSL information bit stream and decoding a corresponding encoded DSL symbol. In accordance with one embodiment, an apparatus for encoding a DSL information bit stream is provided having a switch with an input configured to receive a DSL information bit stream and at least two outputs. An encoder is provided and coupled to a first output of the switch. A serial to parallel converter is provided and coupled to both an output of the encoder and a second output of the switch. Finally, a mapper is provided and coupled to an output of the serial to parallel converter through multiple paths. Preferably, a first coupling path between the serial to parallel converter and the mapper is a direct path and a second coupling path includes a second encoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.