Efficient implementation of a decision directed phase locked loop (DD-PLL) for use with short block code in digital communication systems
US6956924B2 · kind B2 · utility
29Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2001 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | May 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A decision directed phase locked loop (DD-PLL) is efficiently implemented in a communication receiver. The phase locked loop includes an enhanced block decoder inside a phase detector which takes in the baseband complex samples and the current channel phase estimate (or the tracked phase) and generates a feedback phase error term. A loop filter filters the phase error terms and a phase accumulator updates the tracked phase estimate on each iteration of the loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.