Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation
US6957375B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 2004 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Feb 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6362
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus of the present invention can be used to implement a communications system wherein different devices using the same LDPC code can be implemented using different levels of parallelism. The use of a novel class of LDPC codes makes such differences in parallelism possible. Use of a factorable permuter in various embodiments of the invention make LDPC devices with different levels of parallelism in the encoder and decoder relatively easy to implement when using the codes in the class of LDPC codes discussed herein. The factorable permuter may be implemented as a controllable multi-stage switching devices which performs none, one, or multiple sequential reordering operations on a Z element vector passed between memory and a Z element vector processor, with the switching one individual vectors being controlled in accordance with the graph structure of the code being implemented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.