Controlling the propagation of a digital signal by means of variable I/O delay compensation using delay-tracking
US6957399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2002 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Mar 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The propagation of a feedback signal, such as a DQS signal generated in response to a read request in a Double Data Rate (DDR) memory system, into a digital host system, such as an ASIC, is controlled by using delay tracking to compensate for variable I/O delay. The memory system includes a controller and an interface, both on the ASIC, and memory units coupled to the controller through the interface, all configured on a printed circuit board (PCB). The interface uses the read request signal, sent by the controller to initiate read operations, to generate a read-enable signal, which is transmitted to a trace on the PCB one-half cycle of the system clock before DQS is expected to reach the interface. The trace tracks the total delay encountered by the system clock and DQS between the interface unit and memory units, and is routed back to the interface unit, where read-enable is used to generate an enable signal that allows DQS to propagate into the ASIC only when DQS is a valid digital signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.