Method and apparatus for routing nets in an integrated circuit layout
US6957408B1 · kind B1 · utility
11Cited by
104References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2002 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Jan 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the invention provide a method of for routing nets within a region of an integrated circuit (“IC”) layout. The method selects a net in the IC layout region. It then identifies a topological route for the selected net. From the selected net's topological route, this method then generates a geometric route for the selected net.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.