Gridless IC layout and method and apparatus for generating such a layout
US6957411B1 · kind B1 · utility
29Cited by
115References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2002 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Jul 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the invention provide a method of routing nets in a region of an integrated-circuit (“IC”) layout. The method selects a net that has several routable elements. It then defines a route for the net. To define the route, the method uses a wiring model that specifies preferred non-Manhattan wiring directions. It also uses a manufacturing grid as the only grid for constraining the location of interconnect lines for connecting the net's routable elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.