Programmable gain amplifier with glitch minimization
US6958648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2004 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | Aug 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G1/0088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programable gain amplifier (PGA) has an amplifier and a variable resistor that is connected to the output of the amplifier. The variable resistor includes a resistor that is connected to a reference voltage and multiple parallel taps that tap off the resistor. A two-stage switch network having fine stage switches and coarse stage switches connects the resistor taps to an output node of the PGA. The taps and corresponding fine stage switches are arranged into two or more groups, where each group has n-number of fine stage switches and corresponding taps. One terminal of each fine stage switch is connected to the corresponding resistor tap, and the other terminal is connected to an output terminal for the corresponding group. The coarse stage switches select from among the groups of fine stage switches, and connect to the output of the PGA. During operation, one selected tap is connected to the output of the PGA by closing the appropriate fine stage switch and coarse stage switch, where the selected tap defines a selected group of the fine stage switches. Additionally, one fine stage switch is closed in each of the non-selected groups of fine stage switches. In one embodiment, the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.