Matched delay line voltage converter
US6958721B2 · kind B2 · utility
10Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2003 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | Jan 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for measuring or converting voltage, the method comprising: applying an input voltage to a primary delay line; applying a reference voltage to a timer delay line; propagating a delay signal through the primary delay line; propagating a timer signal through the timer delay line; establishing a sampling period based on the timer signal propagation; and measuring an extent of delay signal propagation along the primary delay line during the established sampling period, the measured signal propagation extent being indicative of a difference between the input voltage and the reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.