Method and apparatus for reducing noise in analog-to-digital converter devices
US6958723B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2004 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | Mar 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/447
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter apparatus has a plurality of stages. Each stage includes a residue amplifier having a first and second amplifier unit. Each of the amplifier units has a first input locus, a second input locus and an output locus. The amplifier units cooperate in receiving a differential input data signal at the first input loci. A DC level setting signal unit is coupled with the second input loci and provides a DC level setting current in a first current direction. A counter-current signal generating unit is coupled with the second input loci via a single coupling locus common with the second input loci and provides a control current signal to the second input loci in a second current direction opposite to the first current direction. The control current signal provides a DC level control for each of the amplifier units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.