Staggered compare architecture for content addressable memory (CAM) device
US6958925B1 · kind B1 · utility
23Cited by
14References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 24, 2003 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | Dec 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) device (300) can receive a compare data value having a native word size. The compare data value can be split into smaller portions, with one portion can be applied to a first CAM block (302-0) and another being applied to a second CAM block (302-1) on a subsequent clock (CAMCLK) cycle. Activation of circuit elements in the second CAM block (302-1) can be conditioned on first match results (CMATCHA0 to CMATCHAn) generated by first CAM block (302-0).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.