Device for programmable frequency divider
US6959066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2003 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | Apr 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/662
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a programmable frequency divider having one n-bit adder and one n-bit D Flip Flop. These are used to transform the import clock to the target clock. The adder takes one adjustment parameter and one return signal as a basis to create the first output signal, with the possibility to program the adjustment parameter. The D Flip Flop and the adder create a cycle, which is used to receive the first output signal and its import clock to create the second output signal. The second output signal is separated into a return signal and the target signal. The D Flip Flop sends the return signal back to the adder, which will make addition calculations under the adjustment parameter, finally giving out the target clock with the target signal as a calculation basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.