Reconfigurable processing system and method
US6959378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2001 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | Jun 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed. For each vector, vector address units provide addresses which stride through each element of each vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.