Dual-counterdoped channel field effect transistor and method
US6960499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2004 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Jun 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/235
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed adjacent to the channel. In one embodiment of the present invention, the first doped region (28) is doped with arsenic, while the second doped region (26) is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer (28) allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.