Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same
US6960507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2004 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Jan 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/673
Abstract
A vertical double channel silicon-on-insulator (SOI) field-effect-transistor (FET) includes a pair of two vertical semiconductor layers in contact with a pair of parallel shallow trench isolation layers on a substrate, a source, a drain and a channel region on each of the pair of vertical semiconductor layers with corresponding regions on the pair of vertical semiconductor layers facing each other in alignment, a gate oxide on the channel region of both of the pair of the vertical semiconductor layers, and a gate electrode, a source electrode, and a drain electrode electrically connecting the respective regions of the pair of vertical semiconductor layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.