Methods for sidewall protection of metal interconnect for unlanded vias using physical vapor deposition
US6960529B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2003 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Sep 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76852
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for protecting the sidewall of a metal interconnect component using Physical Vapor Deposition (PVD) processes and using a single barrier metal material. After forming the metal interconnect component, a single barrier metal is deposited on its sidewall using PVD. A subsequent anisotropic etching of the barrier metal removes the barrier metal from the horizontal surface except for some that still remains on the top surface of the metal interconnect layer. A dielectric layer is then formed over the metal interconnect component and the barrier metal. The unlanded via is etched through the dielectric layer to the metal interconnect component, and then filled with a second metal to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.