High speed phase selector
US6960942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2001 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Dec 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and circuitry for selecting phases while avoiding glitches in the output signal during phase switching. An integrated circuit having a plurality of input terminals coupled to receive a respective plurality of clock signals having different phases, and a plurality of control terminals coupled to receive a respective plurality of phase selection signals. The circuit is configured to output a first selected clock signal from the plurality of clock signals in response to a first combination of the phase selection signals, and further configured to switch from the first selected clock signal to a second selected clock signal in response to a second combination of the phase selection signal. The circuit disengages the first clock signal after the second phases selection signal is engaged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.