Digital image processing and data compression circuit
US6961085B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Apr 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/68
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
CCD data is compressed by compression means and stored in a raw image data buffer (step 10). Then, the compressed data is expanded by expansion means, so that pixel data thereof is sequentially output to an RPU (step 11). The RPU executes real-time image processing on the pixel data, so that the processed data is stored in a processed data buffer in units of frames. Then, a CPU reads an image from the processed data buffer at a proper timing and performs software processing such as high-efficiency coding through a temporary storage data buffer, for storing and preserving the processed data in a storage medium (step 12). Thus provided is an image processing circuit capable of reducing the scale of buffer areas in a memory for remarkably reducing the cost for the memory as well as power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.