Digital display jitter correction apparatus and method
US6961095B2 · kind B2 · utility
3Cited by
23References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2001 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Feb 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/21
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.