Random access memory having an adaptable latency

US6961276B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Francois Ibrahim Atallah · Raleigh, US
• James Norris Dieffenderfer · Apex, US
• Jeffrey Herbert Fischer · Cary, US
• Michael T. Fragano · South Burlington, US
• Daniel Stephen Geise · South Burlington, US
• Jeffery H. Oppold · South Burlington, US
• Michael R. Ouellette · Colchester, US
• Neelesh Pai · Williston, US
• William Robert Reohr · Ridgefield, US
• Joel A. Silberman · Somers, US
• Thomas Philip Speier · Holly Springs, US

Key dates

• Filing date: Sep 17, 2003
• Grant date: Nov 1, 2005
• Expiry date: Apr 17, 2024

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C7/06
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers. The memory circuit advantageously provides an adaptable latency by controlling the mode of operation of the circuit.