Priority rules for reducing network message routing latency
US6961781B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Oct 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/522
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method is disclosed for reducing network message passing latency in a distributed multiprocessing computer system that contains a plurality of microprocessors in a computer network, each microprocessor including router logic to route message packets prioritized in importance by the type of message packet, age of the message packet, and the source of the message packet. The microprocessors each include a plurality of network input ports connected to corresponding local arbiters in the router. The local arbiters are each able to select a message packet from the message packets waiting at the associated network input port. Microprocessor input ports and microprocessor output ports in the microprocessor allow the exchange of message packets between hardware functional units in the microprocessor and between the microprocessors. The microprocessor input ports are similarly each coupled to corresponding local arbiters in the router. Each of the local arbiters is able to select a message packet among the message packets waiting at the microprocessor input port. Global arbiters in the router connected to the network output ports and microprocessor output ports select a message…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.