Bus arbiter and bus access arbitrating method
US6961793B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 19, 2002 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Oct 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus arbiter for a group of masters and a bus access control method. An arbitration priority control section output basic priority data for each of the masters. An arbitration priority generating section is provided for each of the masters, and combines the basic priority data for the corresponding master with request indication data indicating existence or non-existing of a bus access request from corresponding master to generate arbitration priority data. An arbitration priority comparing section compares the arbitration priority data for the masters with each other to determine the arbitration priority data which has the highest priority, and outputs a comparison resultant signal containing data for specifying the master corresponding to the arbitration priority data with the highest priority. An arbitration result notifying section outputs a bus use permission signal to the corresponding master with the highest priority in response to the comparison resultant signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.