Reconfigurable cache controller for nonuniform memory access computer systems
US6961821B2 · kind B2 · utility
17Cited by
7References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 16, 2002 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Jul 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/127
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and structure for replacing cache lines in a computer system having a set associative cache memory is disclosed. The method establishes ranking guidelines utilizing a writable cache replacement control array, wherein the guidelines can be dynamically changed by writing data to the cache replacement control array. The invention ranks states of different cache lines according to the ranking guidelines and replaces, upon a cache miss, a cache line having a highest rank of the rankings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.