Globally clocked interfaces having reduced data path length
US6961861B2 · kind B2 · utility
2Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2002 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Jan 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A interface, which connects memory and an integrated circuit, having a write path and read path that allow synchronous data propagation is provided. Further, a method for synchronizing data propagation through a read path and a write path of an interface is provided. The interface uses clock signals and paths based on a clock signal to synchronize the flow of data through various paths within the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.