Dynamic variable-length error correction code
US6961890B2 · kind B2 · utility
159Cited by
7References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 16, 2001 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Oct 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data storage media, such as silicon-based non-volatile memory, are configured according to a data structure containing a payload portion and a redundancy portion. A divider segregating the payload and redundancy portions may be dynamically relocated, thereby altering the size of the redundancy to allow for use of an error correcting code selected to provide the data integrity required in response to changing conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.